Simulation systems are often used for verification and debugging of logic designs. Simulation systems for logic design verification are typically either event-driven or cycle-based. FIG. 1 shows components of a typical cycle-based simulation system for verification of logic designs. A logic design (20) is compiled by a compiler (22) residing on a host computer (24), thereby generating a simulation image file (26), which includes executable code. The logic design may be written in a Hardware Definition Language (HDL), such as Verilog or Very-High-Speed-Integrated-Circuit Hardware Description Language (VHDL). The simulation image file (26) is executed on a simulation system (28). The simulation system (28) may be hardware accelerated and may use multiple processors running in parallel.
One of the most commonly used methods in logic design verification is signal tracing. Signal tracing involves periodically saving values of particular signals of the simulation during runtime. The values of such signals of the logic design at certain times may be of interest to a designer. For example, the designer may wish to examine signal values at the output of a particular NAND gate at particular times/cycles. Typically, the saved signal values are viewed by the designer using a commercial waveform display tool, e.g., SignalScan™, a trademark of Cadence Design Systems, Inc. Thus, by analysis of the saved signal values, the logic design may be debugged.
Two common methods of signal tracing are compile-time tracing and runtime tracing. With compile-time tracing, signals are defined statically by the compiler (22) during compilation of the logic design (20). FIG. 2 shows components of a simulation system using compile-time tracing. The compiler (22) takes inputs from the logic design (20) and tracing information (40). The tracing information (40) includes instructions determining which signals are traced, how to save values of the traced signals, and for what times the signals are traced. The compiler (22) compiles the logic design (20) and the tracing information (40) to generate a simulation image (42), which includes tracing instructions (44). An exemplary size of the simulation image (42) is 10 Megabytes, of which 2 Megabytes is accounted for by the tracing instructions (44).
The simulator (28) executes the simulation image (42) and uploads traced signal information from a traced signal buffer (46) to the host computer (24). The traced signal buffer (46) is a location where the values of traced signals may be stored. The traced signal buffer (46) may be a two-dimensional array, which is created by the compiler (22).
FIG. 3 shows a flowchart for using the simulator of FIG. 2 for a cycle-based simulation using compile-time tracing. A first step of the flowchart includes generating the logic design (Step 70). The logic design may be written in an HDL, such as Verilog. The tracing information for the logic design is generated (Step 72), and the compiler compiles the tracing information and the logic design, thereby generating the simulation image (Step 74). Once generated, the simulation image is loaded onto the simulator (Step 76), and the simulator simulates the logic design and traces the signals for the current cycle (Step 78).
When the current simulation cycle has ended, a determination is made as to whether the simulation (as a whole) has ended (Step 80). If the simulation has ended, the traced signal data is uploaded from the traced signal buffer on the simulator to the host computer (Step 82). Otherwise, if the simulation has not ended, a determination is made as to whether the traced signal buffer is full (Step 84). If the tracing buffer is not full, the simulation advances to the next cycle (Step 90), and the simulation resumes, with the simulation simulating the logic design and tracing signals (Step 78). Otherwise, if the traced signal buffer is full, the simulation is halted (Step 86), and data from the traced signal buffer is uploaded to the host computer (Step 88).
Once data from the traced signal buffer has been uploaded, the simulation advances to the next cycle (Step 90), and the simulation resumes, with the simulation simulating the logic design and tracing signals (Step 78). The simulation continues until the determination at Step 80 indicates that the simulation has ended. If, after the simulation has ended, a user desires to change which signals are traced, Step 72 is repeated, and the simulation begins again.
With runtime tracing, which typically occurs with single-step simulation, signals to be traced during simulation may be defined dynamically by a user of the simulator. FIG. 4 shows components of a simulator using runtime tracing. A compiler (110) takes input from the logic design (20). The compiler (110) compiles the logic design (20) to generate a simulation image (112). An exemplary size of the simulation image (112) is 8 Megabytes. A simulator (114) executes the simulation image (112) and uploads traced signal data (116) to the host computer. A tracing configuration file (118) facilitates input and alteration of tracing information to the simulator. The tracing configuration file (118) includes instructions determining which signals are traced, how to save values of the traced signals, and for what times the signals are traced.
FIG. 5 shows a flowchart for using the simulator of FIG. 4 for a single-step, cycle-based simulation using runtime tracing. A first step of the flowchart includes generating the logic design (Step 140). Once the logic design is generated, the compiler compiles the logic design, thereby generating the simulation image (Step 142). Once generated, the simulation image is loaded onto the simulator (Step 144), and a determination is made as to whether executing the simulation requires tracing signals during the current cycle (Step 146). The tracing configuration file is consulted by the simulator in order to determine whether signals are traced during execution of the current cycle of the simulation.
If signals are not required to be traced during the current cycle, then the simulation is executed on the simulator (Step 148). Otherwise, if signals are required to be traced, then tracing information is obtained (Step 150). Tracing information may be obtained from the tracing configuration file via the host computer. The tracing information may also be obtained from a user of the simulator via a user interface, or other mechanism.
Once the tracing information (if required), is obtained, then the simulation is executed on the simulator and signals are traced (Step 148). After the current cycle has been simulated, a determination is made as to whether tracing information was obtained (Step 152). If signal information was obtained for the current cycle, then signals are traced using the tracing information (Step 154). The tracing information is used to determine which signals are traced. Then, the simulation is halted (Step 156), and traced signal data from the current cycle is uploaded to the host computer (Step 158). The time required for halting the simulation and uploading the saved signal tracing data to the host computer varies with various simulator implementations. For example, halting the simulation and uploading the saved signal tracing data may require 500 milliseconds (ms).
Once the traced signal data from the current cycle is uploaded to the host computer, or, if tracing information was not obtained, as determined in Step 152, the current cycle is advanced (Step 160). A determination is then made as to whether the simulation has ended (Step 162). If the simulation has not ended, Steps 146–162 are repeated until the simulation ends.
Those skilled in the art will appreciate that implementation of, and aspects of, the compile-time tracing and runtime tracing simulators as shown in FIGS. 2–5 may vary according to implementation. For example, although an estimate of 2 MB was given as the amount space that the tracing information adds to the simulation image for compile-time tracing, the amount added to the simulation image by the tracing information may be larger or smaller, according to implementation. Additionally, although an estimate of 500 ms was given for runtime tracing as the amount of time required for uploading saved signal tracing information to the host computer for a simulation cycle, the time added to a runtime tracing simulation for uploading may vary with implementation.